Synopsys DesignWare PVT Subsystem Improves Performance, Power and Lifecycle Management of Silicon on TSMC’s N3 Process Technology
Real-time chip information enables optimized peripheral utilization throughout the silicon lifecycle for key market applications
MOUNTAIN VIEW, Calif., May 27, 2021 / PRNewswire / –
Highlights of this announcement:
DesignWare IP PVT Monitoring and Detection Subsystem supports cutting-edge technologies targeting the AI, Data Center, HPC, Consumer and 5G markets
Innovative and modular architecture offers new sensor technologies for advanced node devices
Designers benefit from a comprehensive PVT subsystem providing real-time information within the chip
Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of its DesignWare® Process, Voltage and Temperature Monitoring and Sensing (PVT) Subsystem IP on TSMC’s leading N3 process technology. The PVT IP Monitoring and Detection Subsystem has been added to the TSMC9000 program, TSMC library and IP quality management program, providing customers with a highly competitive performance advantage for a wide variety of market applications. target, including artificial intelligence (AI), data centers, performance computing (HPC), consumer and 5G. SoC designers targeting TSMC’s most advanced process can use deeply integrated PVT detection and monitoring subsystem technology to assess key chip parameters during production as well as for condition measurement and analysis. dynamics in real time at every stage of the device lifecycle.
In-chip detection from Moortec, now part of Synopsys, continues to be a critical component in achieving the highest levels of performance and reliability in today’s advanced process technologies, underpinning the schematics optimization, telemetry and analysis. The IP address in the subsystem is a fundamental part of Synopsys Silicon Lifecycle Management (SLM) platform. The SLM process begins with placing the sensors embedded in the chip and PVT monitors deep within the chip. The data they provide facilitates a better understanding of chip performance and power activity and enables the analysis engines of the SLM platform to drive more detailed and precise optimizations at every stage of the lifecycle. semiconductors, from the initial design phase to operation in field mission mode.
“TSMC continues to work with our ecosystem partners to address customers’ power and performance design challenges and enable next-generation silicon innovation with design solutions using TSMC’s latest technologies,” said Suk lee, vice president of the Design Infrastructure Management division at TSMC. “The new Synopsys DesignWare PVT monitoring IP protocol is a demonstration of the value of our continued collaboration with Synopsys and will enable continued product support for our mutual customers as they enjoy the power and performance advantages of the process technology.” TSMC N3.
The innovative and modular design of the DesignWare PVT subsystem provides a structure of highly configurable PVT monitors depending on the target application. This latest solution for TSMC N3 process technology includes a distributed thermal sensor enabling highly localized thermal analysis, a new catastrophic trigger sensor for programmable thermal runaway protection, and an additional thermal diode providing independent temperature measurement of the chip even when the chip is powered off. The entire system is controlled by a fourth generation PVT controller which allows easy access to data from multiple instantiations of individual on-board monitors and sensors.
“Driven by the demand for ever increasing design complexity and device gate density, the adoption of PVT monitoring is now critical to the success of advanced node chip design,” said Amit Sanghani, Vice President of Hardware Analytics and Test Group at Synopsys. “DesignWare’s comprehensive suite of integrated PVT monitors and sensors, part of Synopsys’ innovative new Silicon lifecycle management platform, will provide the designer community with innovative integrated sensing technologies, in-depth information about real-time chips and improved product utilization throughout the silicon lifecycle. . “
The DesignWare PVT monitoring and detection subsystem can be configured for specific industry applications and is now available for early customer integration. For more information, visit the DesignWare In-Chip PVT Detection and Monitoring site.
About Synopsys DesignWare IP
Synopsys is a leading provider of high quality and proven silicon IP solutions for SoC designs. DesignWare’s extensive IP portfolio includes logic libraries, integrated memories, PVT sensors, integrated tests, analog IPs, wired and wireless interface IPs, security IPs, integrated processors and subsystems. To accelerate prototyping, software development, and integration of IP into SoCs, Synopsys IP Accelerated initiative offers IP Prototyping Kits, IP SDKs, and IP Subsystems. Synopsys’ significant investment in IP quality, comprehensive technical support, and robust IP development methodology allow designers to reduce integration risk and speed time to market. For more information on Synopsys DesignWare IP, visit https://www.synopsys.com/designware.
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner of innovative companies developing electronic products and software applications on which we rely every day. As a company of the S&P 500, Synopsys has long been a global leader in electronic design automation (EDA) and semiconductor intellectual property and offers the broadest portfolio of testing tools and services. sector application security. Whether you are a system-on-a-chip (SoC) designer creating advanced semiconductors or a software developer writing more secure, high-quality code, Synopsys has the solutions to deliver innovative products. Learn more about www.synopsys.com.
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SOURCE Synopsys, Inc.